Performance Analysis of High Speed Inexact Speculative Adder
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Abstract
A high-speed model of the recent Inexact Speculation Adder(ISA) design is presented in this paper. Also a fine grain pipeline and clock gating is included in this architecture to improve its speed and reduce the power consumption respectively. Simulations of the pipelined ISA, pipelined Speculator, PCLA and pipelined Compensator are presented. The pipelined ISA, pipelined Speculator, pipelined CLA and pipelined Compensator incorporated with the power saving techniques of sleep, stack and sleep stack approaches are also presented. HSPICE is used for stimulation and the required parameters such as delay average power, and power delay products are acquired and presented. It is observed that due to the application of the low power techniques of sleep, stack and sleepy stack, the power delay product has been reduced by 80% compared to the carry-look ahead adder (CLA) based design of ISA.
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