Design of Efficient High Speed Adders For 4-BIT Microprocessor
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Abstract
The building of a Verilog model of a 4-bit microprocessor from fundamental gates and the design of high-speed adder circuits using Xilinx ISE 8.1i are the main topics of this article. To examine the design parameters, the designs are executed on a Field Programmable Gate Array (FPGA). The reason for this inquiry is because an adder is a basic building element of the Arithmetic Logic Unit (ALU) and would be a limiting factor in the Central Processing Unit's performance. We used Verilog and Xilinx ISE 8.1i to simulate and synthesise several adders such as the Ripple Carry Adder, Carry Look Ahead Adder, and Carry Skip Adder in this research work. The architecture's Verilog codes were created with Xilinx ISE 8.1i and aimed for the Xilinx Spartan 3E FPGA. The functioning of high-speed adders is examined, as well as factors such as area and speed
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