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Full adders are the basic building blocks of various circuits like Central Processing Unit (CPU) and Digital Signal Processors (DSP). In this project design and implementation of high speed and efficient MOSFET’s utilization of ALU is going to be done. ALU is the combination of 10T full adder, 10T 16 bit Ripple carry adder and Multiplexer, de-multiplexer and SRAM. All these are implemented and designed using GDI-technique. So, optimizing GDI technique and full adder in terms of delay let us achieve low delay circuits. The architecture utilizes adiabatic inverter for logic level implementation. The modified and proposed architecture designs reduce the stage delay, transistor count. In this complementary pass transistor logic presented and it will used to design a full adder circuit using XOR-XNOR design. From results, it can observe that the 10T full adder will reduce the number of MOSFET’s compared to the 14T full adder. Along with that 10T 16 bit Ripple carry adder and Multiplexer and de-multiplexer and SRAM will reduce the utilization of MOSFET’s. Hence, this project gives effective output.