DESIGN AND IMPLEMENTATION OF MODIFIED VEDIC MULTIPLIER USING HSCG-SCG ADDER

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Usthulamuri Penchalaiah, N.Umadevi, P.Chandupriya, P.Naga Rishitha,N.Sindhuja,Md.Mateen Shareef

Abstract

The Modified Vedic Multiplier is a multiplication algorithm based on ancient Vedic Mathematics principles. The algorithm uses a series of vertical and crosswise calculations to perform multiplication. The Modified HSCG-SCG Adder is an improved version of a conventional binary adder, which uses a decoder to generate partial products and a carry tree to produce the final result. The Modified Vedic Multiplier using Modified HSCG-SCG Adder has advantages over traditional multipliers, such as reduced latency, reduced power consumption, and higher speed. It is suitable for use in applications that require high-speed multiplication, such as digital signal processing, image processing, and cryptography. The implementation of this algorithm can be done using Verilog HDL, a hardware description language. The design can be simulated and tested using a hardware simulator such as Vivado.

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How to Cite
Usthulamuri Penchalaiah, N.Umadevi, P.Chandupriya, P.Naga Rishitha,N.Sindhuja,Md.Mateen Shareef. (2023). DESIGN AND IMPLEMENTATION OF MODIFIED VEDIC MULTIPLIER USING HSCG-SCG ADDER. Turkish Journal of Computer and Mathematics Education (TURCOMAT), 14(2), 454–463. https://doi.org/10.17762/turcomat.v14i2.13675
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Research Articles