DESIGN AND IMPLEMENTATION OF MODIFIED VEDIC MULTIPLIER USING HSCG-SCG ADDER
Main Article Content
Abstract
The Modified Vedic Multiplier is a multiplication algorithm based on ancient Vedic Mathematics principles. The algorithm uses a series of vertical and crosswise calculations to perform multiplication. The Modified HSCG-SCG Adder is an improved version of a conventional binary adder, which uses a decoder to generate partial products and a carry tree to produce the final result. The Modified Vedic Multiplier using Modified HSCG-SCG Adder has advantages over traditional multipliers, such as reduced latency, reduced power consumption, and higher speed. It is suitable for use in applications that require high-speed multiplication, such as digital signal processing, image processing, and cryptography. The implementation of this algorithm can be done using Verilog HDL, a hardware description language. The design can be simulated and tested using a hardware simulator such as Vivado.
Downloads
Metrics
Article Details
Licensing
TURCOMAT publishes articles under the Creative Commons Attribution 4.0 International License (CC BY 4.0). This licensing allows for any use of the work, provided the original author(s) and source are credited, thereby facilitating the free exchange and use of research for the advancement of knowledge.
Detailed Licensing Terms
Attribution (BY): Users must give appropriate credit, provide a link to the license, and indicate if changes were made. Users may do so in any reasonable manner, but not in any way that suggests the licensor endorses them or their use.
No Additional Restrictions: Users may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.