Electronic Device Performance Enhancement through Low-Power, High-Speed IC Design with GDI-Based Carry Look-Ahead Adders

Abstract

The ubiquity of electronic devices, including computers, laptops, mobile phones, and tablets, has led to a growing user base, intensifying demands for improved power efficiency, compactness, energy efficiency, and speed. As engineers, designers, and developers, it is essential to address these parameters to meet user expectations. Various adder design styles, such as Ripple carry adders, carry select adders, carry skip adders, carry look-ahead adders, carry increment adders, carry save adders, and carry bypass adders, are available. While the Ripple carry adder is compact, its computation speed is limited. In contrast, Carry look-ahead and Carry select adders offer enhanced performance. To create high-speed, low-power, and space-efficient integrated circuits (ICs), designers must focus on parameters such as delay time, power consumption, and occupied area. Different logic styles, including static CMOS, dynamic CMOS, dual rail domino logic, pseudo NMOS logic, and pass transistor logic (PTL), are employed to reduce power consumption and improve performance speed. Among these styles, the Gate Diffusion Input (GDI) technique stands out as a powerful approach to reduce power consumption, propagation delay, and transistor counts in digital circuits. However, PTL logic introduces certain output degradation issues. To overcome these challenges, this work deliberately leverages the GDI technique to design logic gates necessary for implementing a Carry look-ahead adder. This approach aims to achieve low power consumption, reduced delay time, energy efficiency, and minimized transistor counts.