Enhancing Integrated Circuit Reliability: Self-Repairing Hybrid Adder with Fault Localization

Abstract

With the ongoing process shrink of integrated circuits and the resulting increase in integration density, the reliability of integrated circuits deployed in the field has become a significant concern. This is especially critical for systems with high stakes, such as server-class computers and embedded systems, where concurrent error detection is of paramount importance. Addition, being the most fundamental arithmetic operation, plays a central role in various Very Large-Scale Integration (VLSI) designs. The reliability of adders is a crucial component in ensuring the overall reliability of these systems. While several techniques have been proposed for concurrent error detection in adders, they primarily focus on detecting errors resulting from single faults. Unfortunately, they do not guarantee the detection of erroneous outputs caused by multiple faults, potentially jeopardizing concurrent error detectability. If a second fault occurs before the detection of the first fault, the system's error detection capability can be compromised. Therefore, it is essential to detect the first fault before a second one occurs to ensure the reliability of adders. This research introduces a novel approach: a self-repairing hybrid adder with built-in fault localization. It combines the advantages of a ripple carry adder and a carry-select adder to mitigate delays and reduce area overhead, while also providing self-repairing properties. This enables the system to not only detect faults but also precisely locate them, facilitating effective self-repairing mechanisms.