DESIGN OF LFSR BASED FAST ERROR-RESILIENT TERNARY CONTENT ADDRESSABLE MEMORY

Abstract

As LFSR based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and Open Flow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of LFSR -based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This extension presents a low-cost and low-response-time technique for the protection of LFSR -based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in LFSR -based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance.