AEROSPACE APPLICATIONS IN NANO SCALE CMOS TECHNOLOGY USING 12T MEMORY CELL

Abstract

Semiconductor sizes and the gaps between them are decreasing with the advancement of technology. This means that SRAM cells used in aerospace applications are more vulnerable to soft-error when the fundamental charge of the fragile nodes decreases. A single-event upset (SEU) caused by a radiation particle striking a sensitive node in a conventional 6T SRAM cell could lead to data inversion. To lessen the consequences of SEUs, this study proposes the use of a Soft-Error-Aware Read-StabilityEnhanced Low-Power 12T (SARP12T) SRAM cell. The performance of SARP12T is evaluated in relation to other recently released soft-error-aware SRAM cells, such as QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. In the event that a radiation attack flips the values of the sensitive nodes in SARP12T, the data may still be recoverable. When a storage node pair initiates a singleevent multi-node upset (SEMNU), SARP12T is resilient enough to endure it. During read operations, the bitline makes it simple to reach the '0' storing memory nodes in the suggested cell, and it also makes them very resilient to interruptions. In terms of energy usage, SARP12T is the most effective holding strategy. SARP12T outperforms competing cells in terms of write performance, and its write latency is much decreased. To achieve all of these advantages, the suggested cell very slightly increases read latency and read/write energy.