Error Resilience in LFSR-Based Ternary Content-Addressable Memory on FPGAs for Packet Classification in SDN and OpenFlow

Abstract

Ternary Content-Addressable Memory (TCAM) based on Linear Feedback Shift Registers (LFSR) serves a crucial role in packet classification for Software-Defined Networking (SDN) and OpenFlow applications on Field-Programmable Gate Arrays (FPGAs). The design of TCAMs on FPGAs predominantly relies on SRAMs to implement TCAM contents. However, SRAMs are susceptible to soft errors, posing a significant challenge in safeguarding LFSR-based TCAMs without compromising critical path delays or impeding search performance. This extension introduces a cost-effective and swift technique for fortifying LFSR-based TCAMs against soft errors. The approach employs straightforward single-bit parity for fault detection, introducing minimal overhead to the critical path. It leverages the binary-encoded TCAM table used for updates in LFSR-based TCAMs to establish a low-response-time error-correction mechanism at minimal cost. Importantly, the error-correction process operates concurrently with lookup operations, thereby preserving high search performance.