Performance analyzes of RNS-FIR filter using prefix accumulation based DA arithmetic

Abstract

This study describes the design of high speed FIR
filter design with low complexity using various types of adders and
multiplication methods. This work also explores the significance
of prefix addition in path delay reduction and it’s accelerating
performance in various DSP applications. The FIR filters consist
of two core functional units such as adder and multiplier. In many
existing FIR filter designs the system performances are
accelerated using various multiplication methodologies and some
optimization techniques. This paper briefly investigates the
necessities of the parallel prefix adder in path delay reductions
and the influence of multiplier less FIR design in overall system
performance. And conclude the performance metrics and trade
off measures between complexity and path delay optimization
level of various types of Prefix adders and multipliers. This work
focuses on both high speed accumulation and multiplication units
for high performance FIR filter design and its performance is
compared with the existing FIR filter design in terms of delay and
hardware utilization rate.