DESIGN A LOW-LATENCY NOVEL FPGA BASED SIGNED MULTIPLIER FOR COMMUNICATION APPLICATIONS

Abstract

The most expensively utilized arithmetic operation in broad range of application is multiplication.
For providing high performance and resource efficient multipliers earlier researches has been presented various accurate and approximate multiplier designs majorly utilized for ASIC (Application Specific Integrated Circuits)- based systems. Though the infrastructural differences among FPGA-based and ASIC system confines the multipliers effectiveness for FPGA (Field Programmable Gate array)-based systems. In addition many of these designs of multiplier are only valid to unsigned numbers. For bridging this gap design of a low-latency novel FPGA based signed multiplier for communication applications is presented in this paper. This multiplier design can be implemented in four steps pre processing, barrel shift register, parallel adder and post processing stages. Partial products are generated in preprocessing stage which are used to realize propagate and generate signals. Then these partial products are shifted and aligned in a sequential order for further computation using barrel shift register. From this barrel shift register partial products are applied to parallel adder structure for the carry generation and propagation. Then final product output can be obtained in the post processing stage by performing the final addition operation. The implementation of presented design is simulated using Xilinx ISE design suit 14.7v software.