A MODIFIED PARTIAL PRODUCT GENERATOR FOR REDUNDANT BINARY MULTIPLIERS

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BALKONDA SHARANYA, T. KAVITHA, Y. DAVID SOLOMON RAJU

Abstract

Approximate computing can decrease the design complication with an increase in
performance and power efficiency for error tolerant applications like multimedia signal processing and
data mining which can tolerate error, exact computing units is not always necessary. They can be
replaced with their approximate counterparts. A new design approach for approximation of multipliers
based on partial products is altered to introduce varying probability terms. A high speed approximate
redundant binary multiplier is designed by using two redundant binary 4:2 compressors. Then
comparison in terms of power, delay, area and signal rate of approximate redundant binary multiplier
(using conventional modified booth algorithm) with high speed approximate redundant binary multiplier
is done using Xilinx tool. In Existing system, Implementation of multiplier comprises three steps
generation of partial products, partial products reduction tree, and vector merge addition to produce final
product from the sum and carry rows generated from the reduction tree. Second step consumes more
power. To reduce power and improve approximate difference, a novel compressor based approximate
multiplier is proposed.

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