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With the view of reducing chip area, Optimization of VLSI Physical Design, region minimization and situation of squares is a significant target in actual plan mechanization of exceptionally huge scope mix chips. The target of limiting the region and arrangement of squares would downsize the size of coordinated chips. An Optimal Solution must be found for actual plan segments like apportioning, floor arranging, arrangement, and directing. This work assists with playing out the streamlining of the benchmark circuits with the above said segments of actual plan utilizing progressive methodology of developmental calculations.