Implementation of Systolic Multiplier Using Hybrid Multiplexer Dependent Adder
Main Article Content
Abstract
Multipliers are basic building blocks in various integrated circuits like microprocessors, micro controllers, and ALUs. The existing multipliers suffer from high power consumption and inefficient use of hardware resources. They often rely on traditional adder structures that are not tailored for specific operations, leading to suboptimal performance. Additionally, their fixed architectures limit adaptability and scalability in different applications. So, the proposed approach offers enhanced computational efficiency and reduced power consumption compared to conventional multiplier designs. By integrating multiplexer-dependent adders into the systolic array, the proposed method optimizes resource utilization and delivers improved performance for various arithmetic operations. This integration allows for dynamic selection of adder types based on the specific multiplication operation, significantly reducing power consumption and latency. By adapting the hardware resources to computational needs, the method achieves higher efficiency and flexibility, making it suitable for a wide range of applications in digital signal processing and data processing systems.
Downloads
Metrics
Article Details
This work is licensed under a Creative Commons Attribution 4.0 International License.
You are free to:
- Share — copy and redistribute the material in any medium or format for any purpose, even commercially.
- Adapt — remix, transform, and build upon the material for any purpose, even commercially.
- The licensor cannot revoke these freedoms as long as you follow the license terms.
Under the following terms:
- Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.
Notices:
You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation .
No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.
References
. Sadhineni, Harika, S. Josaph, and N. Vaishnavi. "Design and analysis of CMOS based multiplier using
LFSR." In AIP Conference Proceedings, vol. 2512, no. 1. AIP Publishing, 2024.
. Srinivas, Chundi Sai, M. S. Manohar, and U. Anusha Rani. "High efficient accurate DL-PO logic multiplier
design for low power applications." In AIP Conference Proceedings, vol. 2512, no. 1. AIP Publishing, 2024.
. Kim, Sunwoong, Cameron J. Norris, James I. Oelund, and Rob A. Rutenbar. "Area-Efficient Iterative
Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers." IEEE Transactions on Very Large
Scale Integration (VLSI) Systems (2024).
. Minaeifar, Atefeh, Ebrahim Abiri, Kourosh Hassanli, Mehrzad Karamimanesh, and Farshid Ahmadi.
"Energy efficient approximate multipliers compatible with error-tolerant application." Computers and
Electrical Engineering 114 (2024): 109064.
. Hui, Yajuan, Qingzhen Li, Leimin Wang, Cheng Liu, Deming Zhang, and Xiangshui Miao. "In-Memory
Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays."
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2024).
. Parmar, Rushik, Khushil Yadav, Gauraangi Anand, and Gaurav Trivedi. "An SNN Inspired Area and Power
Efficient VLSI Architecture of Myocardial Infarction Classifier for Wearable Devices." IEEE Transactions
on Circuits and Systems II: Express Briefs (2024).
. Beura, Srikant Kumar, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi, and Prabir Saha. "Inexact
radix-4 Booth multipliers based on new partial product generation scheme for image multiplication."
Integration 94 (2024): 102096.
. Vakili, Bahareh, Omid Akbari, and Behzad Ebrahimi. "Efficient approximate multipliers utilizing compact
and low-power compressors for error-resilient applications." AEU-International Journal of Electronics and
Communications 174 (2024): 155039.
. Haq, Shams Ul, Erfan Abbasian, Vijay Kumar Sharma, Tabassum Khurshid, and Hanaa Fathi. "EnergyEfficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology." AEU-International
Journal of Electronics and Communications 175 (2024): 155088.
. Rohani, Zahra, and Azadeh Alsadat Emrani Zarandi. "Simulation for a low-energy ternary multiplier cell
based on Graphene nanoribbon field-effect transistor." Int. J. Nano Dimens 15, no. 1 (2024): 49-62.
. Kuo, Chao-Tsung, and Yao-Cheng Wu. "Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on
Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable
Gate Array." Electronics 13, no. 2 (2024): 311.
. Ke, Hongfei, Hao Li, and Peiyong Zhang. "High-performance montgomery modular multiplier with NTT
and negative wrapped convolution." Microelectronics Journal 144 (2024): 106085.
. Balaji, M., and N. Padmaja. "Area and delay efficient RNS-based FIR filter design using fast multipliers."
Measurement: Sensors (2024): 101014.
. Malathi, L., A. Bharathi, and A. N. Jayanthi. "FPGA design of FFT based intelligent accelerator with
optimized Wallace tree multiplier for image super resolution and quality enhancement." Biomedical Signal
Processing and Control 88 (2024): 105599.
. Srinivasarao, G., Penchaliah, U., Devadasu, G. et al. Deep learning based condition monitoring of road
traffic for enhanced transportation routing. J Transp Secur 17, 8 (2024). https://doi.org/10.1007/s12198-
-00271-3
. Yassin, Hoda, Arash Akhoundi, El-Sayed Hasaneen, and Dante G. Muratore. "A Power-Efficient
Oscillatory Synchronization Feature Extractor for Closed-Loop Neuromodulation." IEEE Transactions on
Circuits and Systems II: Express Briefs (2024).