Design of Reconfigurable Logic Block Based Sequential Circuits Using Look Up Table Logics
Main Article Content
Abstract
Reconfigurable sequential circuits find applications in various digital systems, including communication networks, data processing units, embedded systems, and FPGA-based designs. Their ability to adapt and reconfigure their functionality onthe-fly allows them to accommodate dynamic requirements and optimize the use of hardware resources. Traditional implementations of sequential circuits involve static configurations, where the logic and functionality are fixed during synthesis. While these methods are straightforward to design and implement, they lack adaptability and cannot be modified without redesigning the entire circuit. The proposed method involves the utilization of a dedicated Reconfigurable Logic Block (RLB) within the sequential circuits, allowing for dynamic configuration changes without altering the overall circuit structure. The RLB can be programmed to provide different logic functions using look up tables, multiplexers, enabling the sequential circuit such as counters and shift registers to change its behaviour.
Downloads
Metrics
Article Details
This work is licensed under a Creative Commons Attribution 4.0 International License.
You are free to:
- Share — copy and redistribute the material in any medium or format for any purpose, even commercially.
- Adapt — remix, transform, and build upon the material for any purpose, even commercially.
- The licensor cannot revoke these freedoms as long as you follow the license terms.
Under the following terms:
- Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.
Notices:
You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation .
No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.
References
Sanadhya, Minakshi, and Devendra Kumar Sharma. "Study of Adiabatic Logic-Based Combinational and
Sequential Circuits for Low-Power Applications." In Low Power Architectures for IoT Applications, pp.
-84. Singapore: Springer Nature Singapore, 2023.
Govindaraj.V, S. Dhanasekar, K. Martinsagayam, Digvijay Pandey, Binay Kumar Pandey, and Vinay Kumar
Nassa. "Low-power test pattern generator using modified LFSR." Aerospace Systems (2023): 1-8.
Pomeranz, "Testability Evaluation for Local Design Modifications." IEEE Transactions on Very LargeScale Integration (VLSI) Systems (2023).
Angadi, Aditi, Shreya Umarani, Totashri Sajjanar, Rakshita Karnam, Kotresh Marali, and Shrikanth
Shirakol. "Architectural Design of Built in Self-Test for VLSI Circuits using LFSR." In 2023 International
Conference on Applied Intelligence and Sustainable Computing (ICAISC), pp. 1-7. IEEE, 2023.
Chandra, B. Ravi, Chinta Pranitha, Aunupati Ediga Preethi, Konkala Pavani, Mantriki Rajini, and
Houdekari Mounika Bai. "Implementation of Ripple Carry Adder Using Full Swing Gate Diffusion Input."
In 2023 7th International Conference on Trends in Electronics and Informatics (ICOEI), pp. 44-50. IEEE,
Priyadarshini, V., M. Manaswini, M. Krishna Babu, and M. Mallika. "DESIGN OF LOW POWER AND
HIGH-SPEED CMOS D-FLIPFLOP USING HYBRID LOW POWER TECHNIQUES."
Sanadhya, Minakshi, and Devendra Kumar Sharma. "D flip-flop design by adiabatic technique for low
power applications." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 1 (2023):
-146.
Shah, Owais Ahmad, Geeta Nijhawan, and Imran Ahmed Khan. "A glitch free variability resistant high
speed and low power sense amplifier-based flip flop for digital sequential circuits." Engineering Research
Express 5, no. 3 (2023): 035046.
Hu, Yinghua, Yuke Zhang, Kaixin Yang, Dake Chen, Peter A. Beerel, and Pierluigi Nuzzo. "On the Security
of Sequential Logic Locking Against Oracle-Guided Attacks." IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems (2023).
Ramakrishnan, Kannan, and K. Vidhya. "Design and Optimization of Sequence Generator Using NN
Transvidkan Gate." (2023).
Harikrishna, A., Chowdamjollu Sai Siddartha, Kokollu Venkatesh, Guduru Bose, and Burla Bhuvan Shyam
Reddy. "A LOW POWER BINARY SQUARE ROOTER USING REVERSIBLE LOGIC." Turkish Journal
of Computer and Mathematics Education (TURCOMAT) 14, no. 2 (2023): 435-443.
NOUSHEEN, MD SANA, and T. VIJAY KUMAR. "IMPLEMENTATION OF LOSSLESS IMAGE
COMPRESSION USING FUZZY BASED MODIFIED GOLOMB RICE ENCODING." Journal of
Engineering Sciences 14, no. 02 (2023).
Geonhwi, Bomin Joo, and Bai-Sun Kong. "CMOS Clock-Gated Synchronous Up/Down Counter with HighSpeed Local Clock Generation and Compact Toggle Flip-Flop." IEEE Transactions on Circuits and Systems
I: Regular Papers (2023).
Moraitis, Michail. "FPGA Bitstream Modification: Attacks and Countermeasures." IEEE Access 11 (2023):
-127955.
Srinivasarao, G., Penchaliah, U., Devadasu, G. et al. Deep learning based condition monitoring of road
traffic for enhanced transportation routing. J Transp Secur 17, 8 (2024). https://doi.org/10.1007/s12198-
-00271-3
Irith. "Test Data Compression for Transparent-Scan Sequences." IEEE Transactions on Very Large-Scale
Integration (VLSI) Systems 31, no. 4 (2023): 601-605.