A LOW POWER BINARY SQUARE ROOTER USING REVERSIBLE LOGIC

Abstract

Square root is a vital mathematical operation which has a lot of applications. Square rooters are used in computer graphics, global positioning system (GPS), digital signal processing (DSP) computations, mathematical calculations, and data processing. In the present world of developments in various fields, the main novelty in the field of VLSI is Low Power. To attain low power Reversible logic is used in this design. In Irreversible logics, the amount of output port and input ports are not uniform and therefore they will be a loss of information bits. In restoring method more hardware resources are required whereas in non-restoring method it consumes less hardware compared to restoring method. Hence non-restoring algorithm is preferred. Many hardware architectures for digit-by-digit square root calculation using irreversible logic have been proposed. There are many reversible logic circuits that are used for the computation. Power reduction can also be done using array based arithmetic computation. Reversible logic is used to design hardware realization of non-restoring algorithm for computation of square root. Power obtained was high.The binary square rooter is designed and implemented using RCSM (Reversible Controlled Subtract Multiplexer). For further development such as number of quantum cost, garbage outputs and the constant inputs, binary square rooter is implemented using SRG (Samiur Rahman Gate). Binary square rooter using non-restoring algorithm is designed using both SRG and conventional approach