Design of Area Efficient Low Power Ever Mixed Logic Line Decoders and Comparator

Abstract

Mixed logic designs take a prioritized place in logic design approaches which will give a simplified mechanism for the analysis of digital circuits. The right utilization of mixed logic notation produces logic expressions and logic relations that are analogs of each other. Also, a mixed logic implementation gives clear idea with regards to the activity of a circuit. Here in this article, we introduced mixed logic designs like pass transistors (DVL), transmission gate (TGL), static CMOS. By using CMOS technology, it requires 20 transistors to design 2:4-line decoder but by using this mixed logic we can design the same 2:4-line decoder with the use of 14 transistors (14T) only. Furthermore, 4:16 line decoders are designed with this novel mixed logic topologies. Introducing mixed logic approach a 2-bit comparator was designed by using 4:16 line decoder mixed logic. All proposed circuits have a smaller number of transistors and designed by using novel topologies, these logics proves in reducing the transistors count, power, and delay in a satisfying level. Finally, a variety of simulations are carried using DSCH and MICROWIND tools at 7nm range to examine all notable changes in parameters.