Low Power Binary Square Root Calculation through Reversible Logic Architectures

Abstract

The square root operation holds great mathematical significance and finds applications in various fields, including computer graphics, global positioning systems (GPS), digital signal processing (DSP), mathematical computations, and data processing. In the context of today's advancements, the primary focus in Very Large-Scale Integration (VLSI) design is minimizing power consumption. To achieve low power consumption, reversible logic is employed in this design. In contrast to irreversible logics, where the number of output and input ports may not be uniform, leading to information loss, reversible logic offers a solution. Additionally, it consumes fewer hardware resources compared to restoring methods, making it a preferred choice. Numerous hardware architectures have been proposed for digit-by-digit square root calculations using irreversible logic, and several reversible logic circuits are employed for such computations. This research aims to leverage reversible logic to design a hardware realization of the non-restoring algorithm for square root computation, with a focus on power reduction. The implementation of a binary square rooter is achieved using the Reversible Controlled Subtract Multiplexer (RCSM). Furthermore, for further development and optimization, considerations such as quantum cost, garbage outputs, and constant inputs, a binary square rooter is implemented using the Samiur Rahman Gate (SRG) alongside the conventional approach.