DESIGN OF A 2-BIT MAGNITUDE COMPARTOR USING MULTIPLEXER USING PTL

Abstract

Design of a 2-bit binary Magnitude Comparator (MC) is presented in this research. The proposed MC has been designed using Conventional CMOS (CCMOS) logic, Pass Transistor Logic (PTL). The design is simulated along with 5 other existing MC designs to carry out evaluation and comparison. The proposed 2-bit MC displayed satisfactory level of improvement in speed and power. For this reason, significant enhancement in Power Delay Product (PDP) could have been attained. Due to the significant enhancement in performance, the proposed MC can be considered as a highly effective alternative to the existing MC designs. The rapid changes in circuit design have bring about various design methodologies for VLSI circuit implementation such as CCMOS, PTL, Transmission Gate Logic (TGL) etc. For this reason, various MC designs have been invented. PTL 2-bit MC is implemented using 40 transistors. PTL based design has a major disadvantage: voltage degradation. This voltage degradation problem becomes quite severe in lower CMOS technology nodes. For this reason, designs solely implemented using PTL without swing restoring transistors have become quite limited nowadays. This voltage degradation leads to another major problem: weak drive power. Due to various issues related to PTL, new designs have emerged