DESIGN AND IMPLEMENTATION OF A HIGH SPEED AND AREA EFFICIENT VLSI ARCHITECTURE OF BINARY ADDER
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Abstract
In this paper design and implementation of a high speed and area efficient VLSI architecture of
binary adder is implemented. Basically, adders plays very important role in DSP (Digital Signal Processing) and micro processor applications. Input „a‟ and input „b‟ are assigned in particular order. Next preprocessing stage will be performed. In pre processing stages both propagator and generator signals are generated. Propagator and generator unit generate the signals of propagate and generate. Black cell and grey cells are generated in Carry generation unit. Addition is performed using adder tree block. At last output is saved in post processing stage. From results it can observe the RTL (Register Transfer Logic) schematic, Technology schematic of proposed system. Hence the binary adder gives effective results.
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