Performance of Hybrid Connected Network on Chip Router to Improve Latency and Throughput
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Abstract
The design of Network-on-Chip (NoC) routers plays a critical role in ensuring efficient data transmission. This project presents an innovative approach to designing NoC routers that prioritize area efficiency. It introduces a hybrid scheme tailored for NoCs, aiming to significantly reduce latency and power consumption. Existing NoC architectures typically employ either circuit switching or packet switching techniques, each with its own limitations. Circuit switching can lead to high latency due to setup time, while packet switching suffer from increased power consumption and congestion. To address these drawbacks, our proposed hybrid scheme combines virtual circuit switching with existing circuit and packet switching methods. By allowing multiple virtual circuit-switched (VCS) connections to share a common physical channel, our approach optimizes resource utilization and minimizes latency, Throughput. Furthermore, the integration of virtual circuit switching introduces dynamic routing flexibility, enhancing adaptability to varying traffic conditions. Hence, this work shows the superior performance and efficiency of our hybrid scheme compared to traditional NoC architectures
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