Design and Analysis of Low-Power Full Adder using Novel 10-T XOR-XNOR Cell
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Abstract
Many electronic devices are mostly used by the many humans and these become more important in our daily life. These electronics will have mostly comprised arithmetic circuits. For the multipliers, the adder is a traditional component for most of the circuits. Arithmetic circuits are significantly utilized by the data paths that uses one-third of power in the high-performance microprocessors. It is very important to enhance the performance of the adders which increase the overall performance significantly. To implement full adder (FA) circuits, hybrid logic is most widely used. The performance of hybrid FA is calculated in terms of delay, power, and driving capability is mostly dependent on the performance of XOR–XNOR circuit. In this paper, a high speed, low-power 10-T XOR–XNOR circuit is proposed, which provides full swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it Tanner EDA environment.
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