Design Of Multiport Memory For Consumption Of Less Energy

Abstract

The utilization of Block RAMs (BRAMs) makes a critical performance factor for multiport memory excessive demand on block of BRAMs. The  BRAMs usage from other parts of a design limits the operatind frequency, as does the dynamic routing between BRAMs and logic. A more effective way of using a standard two reads one write (2R1W) memory as a 2R1W/4R memory has been introduced with the introduction of a brand new perspective of BRAM.  Exploitation of the 2R1W/4R as the building block, gives introduction to 4R1W memory hierarchical design that requires 25% fewer BRAMs when compared to the previous approach of 2R1W module duplication. With the 2R1W/4R memory and the hierarchical 4R1W memory, more read/write ports can be added.  The efficient approches of BRAM can achieve higher clock frequencies for complex multiport designs by reducing the complexity of routing in an FPGA.  From the proposed 2R1W/4R memory to the hierarchical 4R1W memory,  more read/write ports memories have the capacity to expand. In this work, design of multiport memory are carried out using the register bank and the communication are sent to the processor. The results are once again stored back to the multiport memory. The simulation results are observed using the model sim software