Implementation of Wallace Tree Multiplier Using 8:4 Compressor
Main Article Content
Abstract
Multipliers are prime scheme implementation of Microprocessors, VLSI and Embedded Systems. Regrettably, Multipliers are designate by compound function represent and constitute one of the supreme power consuming digital blocks. Estimate computing is an Emerging trend in VLSI design. Now a day the Multiplier is a vital role in most research and development areas. In this paper, the Implementation of Wallace tree Multiplier using 8:4 Compressor is done. The multiplier design will be made by 8:4 Compressor that reduces the power consumption than the optimized compressor design. The proposed 8:4 Compressor is implemented using AND and OR gates.
Article Details
Issue
Section
You are free to:
- Share — copy and redistribute the material in any medium or format for any purpose, even commercially.
- Adapt — remix, transform, and build upon the material for any purpose, even commercially.
- The licensor cannot revoke these freedoms as long as you follow the license terms.
Under the following terms:
- Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.
Notices:
You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation .
No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.