Power Efficient Clock Pulsed D Flip Flop Using Transmission Gate

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S. B. Prakalya , et. al.

Abstract

The need for low-power sequential circuits is pushing towards the implementation of low power consuming basic memory elements like D Flip-Flop. To accomplish power efficient D Flip-Flop, 180 nm CMOS technology is utilized to develop a novel eminent performance Current-Mode Pulse Triggered D Flip-Flop. Instead of voltage utilization in clock distribution is the new idea in the developed method uses current to render low power consumption clock signal. D Flip-Flop is designed by transmission gate which is also reduces the power consumption along with Current-Mode signaling. The Cadence - Virtuoso tool is to be used to simulate all the circuits with 180nm technology. Power consumption reduction in the designed D Flip-Flop is the foremost and major aim of the project. For reducing, power consumption in D Flip-Flop we are employing two methods. They are, Use of Current Mode Clock Distribution Networks (CM-CDN) instead of Voltage Mode Clock Distribution Networks (VM-CDN). Use of Transmission Gate Logic to implement the D Flip-Flop, instead of Static CMOS Logic.


 

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How to Cite
et. al., S. B. P. , . (2021). Power Efficient Clock Pulsed D Flip Flop Using Transmission Gate. Turkish Journal of Computer and Mathematics Education (TURCOMAT), 12(11), 1544–1555. https://doi.org/10.17762/turcomat.v12i11.6082
Section
Research Articles