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There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butterfly structures for the reduction of complex multipliers presented. Implementations of 32 bit floating point multiplier and floating point adder are presented by using single precision and compare the synthesis results with conventional system. In order to reduce the error we used floating point arithmetic for the butterfly structure. Energy efficient multiplier based on modified booth algorithm is used in radix-2 butterflies. By adopting this architecture the FFT/IFFT implementation using Xilinx FPGA Vertex-7 will improve the 25% logic utilization and the reduction in space utilization. Using arithmetic reduction the power delay product for radix 2 butterfly is reduced by 2.5% compared to normal implementation.
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