Optimized Counter Design for Accelerated Summation in Digital Signal Processing Systems
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Abstract
Efficient summation of multiple operands in parallel is crucial in various digital signal processing units. Accelerating this summation process requires high compression ratio counters and compressors. This study introduces a novel approach to fast saturated binary counters and exact/approximate (4:2) compressors utilizing sorting networks. The counter's inputs are asymmetrically divided into two groups and processed through sorting networks to produce reordered sequences, efficiently represented by one-hot code sequences. By establishing three special Boolean equations between the reordered sequence and the one-hot code sequence, the output boolean expressions of the counter are significantly simplified. Simulation results demonstrate the superiority of the proposed method over conventional approaches in terms of performance.
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