Low Power Logic Gate cell design and its performance analysis
Main Article Content
Abstract
This paper describes the design of a 45nm CMOS technology logic gate library cells for highly energy-efficient applications of
embedded processors. Design of OR and AND, circuits is present in this paper, to improve the speed and power. The comparative analysis of different performance parameters for CMOS logic gates is presented. Average power, Static Power and Delay are the parameters evaluated using Cadence tool. For a full-chip implementation of low-power systems operating at ultra-low voltage is feasible. The power and delay is extracted for logic cells at supply voltages 0.8 V, 1.0 V & 1.2 V at different frequencies
Downloads
Metrics
Article Details
You are free to:
- Share — copy and redistribute the material in any medium or format for any purpose, even commercially.
- Adapt — remix, transform, and build upon the material for any purpose, even commercially.
- The licensor cannot revoke these freedoms as long as you follow the license terms.
Under the following terms:
- Attribution — You must give appropriate credit , provide a link to the license, and indicate if changes were made . You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.
Notices:
You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation .
No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material.
