DESIGN AND IMPLEMENTATION OF AREA EFFICIENT PIPELINED FFT PROCESSOR
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Abstract
In this paper the design and implementation of area efficient pipelined FFT processor is
implemented. Basically FFT supports the bit size which is suitable to the system and mostly used in long term evolution systems. Transport triggered architecture is utilized to customize the size of fault free FFT processor. The inputs 1 and 2 are controlled by control unit. Input 1 performs the addition operation and input 2 performs the multiplication operation. Address generation unit will generate the address for both input 1 and input 2. Radix-2 FFT processor will process the entire data by generating address. Twiddle factor will increase the speed of operation. Hence all the data will be saved in memory unit. At last from simulation result it can observe that reconfigurable memory based FFT processor gives effective outcome
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