Design and Verification for I2C interface protocol Using System Verilog
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Abstract
Today’s world has reached a goal in which complete module can be instigated on a one chip called SOC (system on chip).Protocols are required to combine these components. One such simple and emerging development protocol is the I2C protocol. I2C uses only two initial fundamentals bidirectional buses of pull up resistors configuration i.e Serial Clock Line (SCA) and Serial Data line (SDL). This protocol provides an efficient & simple method of data transaction among the devices & also support multiple masters, bi-directional serial bus used for quicker to connect with each other devices and no loss of data. System Verilog and its verification is used for designing the real time I2C controller with help of mentor graphics tool by creating test bench environment. Code coverage and functional coverages are the two verification coverage matrices in this environment. DUT achieved 93.3 percentage of code coverage and 100 percentage functional coverage achieved for the data and address parameters. The Benefit of this protocol is ; by using Ultra-Fast mode technique data transfer rate can be improved and its low wiring. In this paper explain about the design of an I2C protocol between a slave and master and its verification by using system Verilog language.
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