Design and Analysis of systolic Array for Convolution Neural Networks
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Abstract
Convolutional neural networks (CNN) are used in many functions mainly Digital signal processing (DSPs), Networking, Image and video classification for its accuracy. CNNs need huge estimation and support. To fix hardware, Convolutional neural network accelerators required to be enhanced to bring down size of the memory, resource utilization and power usage. In this paper, the systolic array with Multiply-Accumulate unit (MAC) is designed. The input image of 128x128 size is considered and processed through main memory to systolic array. The systolic array performs the MAC unit operations rows and columns wise. The work is carried out using Xilinx ISE 14.7 environment and synthesised on Artix-7 FPGA.
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