Ultra-Low Power Heterojunction Dopingless -Tunnel FET (HD-TFET) Design and Characterization with SiO2/HfO2 Gate Stacking for High Current Drive

Abstract

A Heterojunction Dopingless TFET model with gate stacking has been presented for ultra-low power application using 2D layered material in the source-region to enhance the bandgap mechanism and thereby tunnelling probability. A layered phosphorene material (B-Ph) with moderate value of bandgap and low effective mass is used in the present work which also adds on in the characterization of proposed source-region of the SOI (silicon-on-insulator) heterojunction doping-less TFET (HD-TFET). The drain current expression is extracted by analytically integrating the band-to-band tunnelling generation rate over the channel thickness. High-ᴋ HfO₂ has been layered on the top of SiO₂ to get a significant and effective gate oxide thickness, which results in the smaller OFF current (improved subthreshold conduction phenomenon) and offers an extremely low subthreshold swing of 1.8 mV/Decade. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, Subthreshold Swing and I_ON/I_OFF than the conventional TFET devices. ATLAS^TM, a two-dimensional (2D) device simulator from Silvaco has been used in the device structure modelling and characterization. The numerical simulation of the proposed device is performed on. The device offers promising ON-OFF transition profiling with ratio of . The small signal behaviour of the proposed HD-TFET model has also been investigated and the performances of the B-Ph/Si gate stacked HD-TFET are observed promising for the possible implementation at circuit level.