Vlsi Implementation Of Multiply And Accumulate Unit Using Offset Binary Coding Distributed Arithmetic

Abstract

In general, Digital Signal processors are designed with Harvard architecture which in turn comprises a special block called Multiply and Accumulate unit (MAC).  The speed improvement of any processor can be done by improving the speed of the dedicated Multiply and Accumulate unit. Offset binary coding based Distributed Arithmetic (DA) is a compelling technique that improves the area, delay, and power trade-off in designing of MAC core, and which in-turn adds the benefits to digital signal processor design. Also introduced the mathematical concepts which lead to offset based Distributed arithmetic are shown below. The different optimization techniques of offset based Distributed Arithmetic based MAC core is synthesized and implemented for efficient implementation of inner product generation. Implementation of different Offset based distributed architectures such as LUT  based four-term & two-term, single LUT inner product computations are compared with LUT-less based architecture are done. The conclusion drawn from this research work is demonstrated on 16-bit MAC cores using offset binary coding distributed arithmetic architectures using Xilinx ISE 14.7 and verified functionality using simulation results. The design is synthesized to know the area, delay, power and energy issues. The offsent based Distributed Airthmetic is compared with its counterparts. Based on the analysis it is found that LUT-LESS can save the power delay product of 7.33% over LUT based when the worst case margin is considered with 1.754% of area reduction.