Floating-Point Multiply and Accumulate Unit Core using Distributed Arithmetic for DSP Applications

Abstract

The main purpose of this article is to reduce the area and power of floating-point multiplication and accumulation units using distributed arithmetic Typically, Multiply and Accumulate unit, multiplier contains partial products.  The speed of the multiplier is important in the MAC unit which decides critical path, as well as area, is additionally of amazing performance in the designing of MAC. The Multiply and Accumulate unit occupies more space and more power. So to overcome these shortcomings, a technique of  Distributed Arithmetic is incorporated. Considering the DA method which replaces the MAC with pre-calculated results about to store in lookup tables. The foremost advantage of DA is it consumes low power and low area. So the area and power of the Multiply and Accumulate unit is reduced. The complete implementation of the Distributed Arithmetic-based Multiply and Accumulate unit is designed using Floating Point operator. In most cases, floating-point adders and multipliers are shown in single precision IEEE-754 format. Implementation of actual DA with different architectures use in a traditional lookup table (LUT) based DA architectures such as DA based implementation with single LUT, Reduction of LUT size using two-bank coefficient partitioning and four-bank coefficient partitioning,Combination of LUT & an adder, and Adder-based DA implementations for inner-product computation. The performance evaluation of different DA-based floating-point MAC can be further evaluated. Finally, Compared the overall performance of DA-based floating-point MAC techniques in terms of area and delay. The designs are modeled using Verilog HDL and are verified by using Xilinx ISE 14.5 and ISIM simulator.