The Energy-Efficient Routing for Ant Colony Optimization in VLSI Design

Abstract

Due to the rapid advancement and growth in Very Large Scale Integrating VLSI design posed a number of challenges. With an increasing number of transistors in a chip, reducing power consumption is a very important goal and a major priority for designers to increase efficiency. The efficient development of a system with a billion chips and blocks on a printed circuit board requires extensive it is important to optimize the usage of different design areas such as chip size, component separation, interconnecting length. Optimizing the Routing phase in the VLSI design cycle is a very important option to reduce power consumption in VLSI design. The role of the routing process is to determine the shortest paths to connect between the chip components. Reducing wire lengths is very important because it leads to reducing the capacitance of the chip and hence power consumption. There are many algorithms that try to decrease wire lengths and decrease capacitance like
Ant Colony Optimization(ACO), Artificial Bee Colony (ABC), Particle Swarm Optimization (PSO). In this paper we will try to improve Ant Colony Optimization (ACO) algorithm to remove some of the limitations of the original ACO algorithm. ACO algorithm used to find optimal routes with minimum capacitance for interconnect routing on VLSI chips.