ECC Processor for Design and Implementation of High- Speed RSD

Main Article Content

Dharmendar Bochu, ImmadisettyVenkata Prakash, Kale JyothiJeevana

Abstract

In this paper, an exportable application-particular guideline set elliptic curve
cryptography (ECC) processor in view of excess marked digit portrayal is
proposed. The processor utilizes broad pipelining methods for Karatsuba– Ofman
strategy to accomplish high throughput duplication. Besides, an effective
measured snake without correlation and a high throughput secluded divider, which
brings about a short data path for expanded recurrence, are executed. The
processor bolsters the suggested NIST curve P256 and depends on an expanded
NIST decrease plot. The proposed processor performs single point augmentation
utilizing focuses in relative directionsin less time.

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How to Cite
Dharmendar Bochu, ImmadisettyVenkata Prakash, Kale JyothiJeevana. (2021). ECC Processor for Design and Implementation of High- Speed RSD. Turkish Journal of Computer and Mathematics Education (TURCOMAT), 10(3), 787–795. https://doi.org/10.17762/turcomat.v10i3.11571
Section
Research Articles