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The demand for high performance Wireless Sensor Network(WSN) is growing and its power dissipation has scarce the life of WSN. Wireless Sensor Network(WSN) needs the development with power efficient deployment. In WSN sensor nodes are remotely placed with inadequate energy budget, so this proposed work mainly focus development of an effective power saving scheme for wireless sensor node using FPGA configurable architecture. Design and implementation of hybrid power management scheme (DVFS + Clock gating) is presented in this paper. It performs functionalities like to activate power management unit as per the state of application tasks under execution. In this work, the power consumption of proposed implementation on FPGA for sensor node is compared with the power consumption of the processor based implementation of sensor nodes. The obtained result shows that the power consumption of hybrid power management technique is drastically reduced
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