A Novel Fault Zone Tiling Approach Based Error Correcting and Detecting Method for Network on Chip Design

Abstract

The behavior of System-on-Chip (SoC) is complicated because they have multiple processors that communicate with each other through concurrent interconnects, such as Network-on-Chip (NoC). It is difficult to debug such SoCs based on a classification of debugging scope and granularity. The lack of observability of internal operations during emulation and post-silicon validation of networks-on-chip (NoCs) makes it difficult to detect and debug functional bugs. Tests that exercise the control-flow portion of the NoC's functionality while abstracting the data content of traffic are required to verify its correctness. The limited trace port bandwidth and buffer size limit the effectiveness of at-speed silicon debug, necessitating very efficient data compression solutions. Because unknown ‘X' values are almost always present in silicon debugging, trace compressors must include an X-tolerance features to avoid significantly reducing error detection capability. To address this issue, this paper introduces X-Tracer, a novel  reconfigurable X-tolerant trace compressor that can tolerate as many X-bits as possible while maintaining a huge compression ratio with low cost of additional design-for-debug hardware. This work also included fault zone protection based on Tiling so as to prevent incorrect rechecking. The proposed project was coded in HDL and simulated with Xilinx