Implementation of FIR Filters through Inner product Units and Parallel Accumulations

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P.V. Krishnarao
Dasari Vandana
Bokkisam Venkata Manasa
Dasari Pavanim
Guntumadugu Pavani Harshitha

Abstract

Finite Impulse Response (FIR) filters are pivotal in digital signal processing, finding applications in diverse fields like audio processing, telecommunications, and biomedical signal analysis. This work presents an enhanced implementation methodology for FIR filters utilizing inner product computation and parallel accumulations. In the existing, FIR filters are typically implemented using convolution techniques, basic adders, and multipliers, which involve sequential processing and intensive computational resources. This method often leads to latency issues and limits real-time applications. Moreover, traditional implementations suffer from inefficiencies in utilizing hardware resources optimally, leading to suboptimal performance. The proposed methodology overcomes these limitations by leveraging inner product computations and parallel accumulation techniques. By exploiting inherent parallelism in the filtering process, the proposed method significantly reduces latency and enhances throughput.

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How to Cite
Krishnarao, P., Vandana, D. ., Manasa, B. V., Pavanim, D. ., & Harshitha, G. P. . (2024). Implementation of FIR Filters through Inner product Units and Parallel Accumulations. Turkish Journal of Computer and Mathematics Education (TURCOMAT), 15(1), 212–217. https://doi.org/10.61841/turcomat.v15i1.14614
Section
Research Articles

References

. Yadav Ranjeeta, Surekh Ghangas, Krishna Kumar Verma, Divyanshu Joshi, Harsit Yadav, and Anmol Dev.

"IMPLEMENTATION OF EFFICIENT FIR FILTER." International Development Planning Review 22, no. 2

(2023): 9-20.

. Syamala Devi, P., D.Vishnupriya, G. Shirisha, Venkata Tharun Reddy Gandham, and Siva Ram Mallela.

"Design of High Efficiency FIR Filters by Using Booth Multiplier and Data-Driven Clock Gating and Multibit

Flip-Flops." In International Conference on Communications and Cyber Physical Engineering 2018, pp. 319-

Singapore: Springer Nature Singapore, 2023.

. Iqbal, JL Mazher, G. Narayan, T. Manikandan, M. Meena, and Jose Anand. "Low power and low area multiplier

and accumulator block for efficient implementation of FIR filter." In Low Power Designs in Nanodevices and

Circuits for Emerging Applications, pp. 267-282. CRC Press.

. Gayathri, S., S. Esha, Challa Bhavya, and Yasha Jyothi M. Shirur. "Design and Implementation of Arithmetic

based FIR Filters for DSP Application." In 2023 International Conference on Intelligent and Innovative

Technologies in Computing, Electrical and Electronics (IITCEE), pp. 782-787. IEEE, 2023.

. Kumar, A. Ramesh, Aruru Sai Kumar, K. Hemanth Lakshmi Phani Prasad, B. Sriraj, and P. Raja Rajasri. "High

performance FIR Architecture for EOG Signal Noise Supression." In 2023 14th International Conference on

Computing Communication and Networking Technologies (ICCCNT), pp. 1-6. IEEE, 2023.

. Shanthi, G., Aruru Sai Kumar, Md Masood Hasan, H. Tanuja, and Ch Yashwanth. "An Efficient and High

Speed FIR Filter using BEC with MUX Technique." In 2023 3rd International Conference on Advances in

Computing, Communication, Embedded and Secure Systems (ACCESS), pp. 256-262. IEEE, 2023.

. Rao, K. Anjali, and Neetesh Purohit. "Hardware Efficient 2-Parallel and 3-Parallel Even Length FIR Filters

Using FFA." In 2023 IEEE 8th International Conference for Convergence in Technology (I2CT), pp. 1-5. IEEE,

. Baker, Timothy, and John P. Hayes. "Design of Large-Scale Stochastic Computing Adders and their Anomalous

Behavior." In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6. IEEE,

. Balaji, M., N. Padmaja, P. Gitanjali, Saif Ali Shaik, and Siva Kumar. "Design of FIR filter with Fast Adders

and Fast Multipliers using RNS Algorithm." In 2023 4th International Conference for Emerging Technology

(INCET), pp. 1-6. IEEE, 2023.

. Biswas, Neelesh, Supriya Dhabal, and Palaniandavar Venkateswaran. "Analysis of Area Efficient Parallel FIR

Filters using FPGA." In 2023 14th International Conference on Computing Communication and Networking

Technologies (ICCCNT), pp. 1-5. IEEE, 2023.

. Bhagavatula, Venkata Vaibhav, and S. V. N. L. Lalitha. "Optimization of FIR filter parameters using forest

optimization algorithm." In AIP Conference Proceedings, vol. 2512, no. 1. AIP Publishing, 2024.

. Farag, Mohammed M. "Design and Analysis of Convolutional Neural Layers: A Signal Processing

Perspective." IEEE Access 11 (2023): 27641-27661.

. Palau, Roberta de Carvalho Nobre, Wagner Penny, Ramiro Viana, Jones Goebel, Guilherme Correa, Marcelo

Porto, and Luciano Agostini. "High-Throughput Hardware Design for the AV1 Decoder Switchable Loop

Restoration Filters." Journal of Integrated Circuits and Systems 18, no. 1 (2023): 1-12.

. U. Penchalaiah and V. S. Kumar, "Design and Implementation of Low Power and Area Efficient Architecture

for High Performance ALU", Parallel Processing Letters., vol. 32, no. 01n02, pp. 2150017, 2022.

. Li, Wenlu, Li Pei, Bing Bai, Jianshuai Wang, and Jingjing Zheng. "Optical filter with on-chip photonic

reservoir computing neural network." In 2023 8th International Conference on Intelligent Computing and Signal

Processing (ICSP), pp. 1251-1255. IEEE, 2023.

. Fornt, Jordi, Leixin Jin, Josep Altet, Francesc Moll, and Antonio Rubio. "Evaluation of the Functional Impact

of Approximate Arithmetic Circuits on Two Application Examples." In Design and Applications of Emerging

Computer Systems, pp. 421-451. Cham: Springer Nature Switzerland, 2024.