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S Naresh Kumar
Dr. Mahesh Kaumr Porwal


In today's VLSI design, static or leakage power consumption is a crucial metric due to component shrinkage. This research proposes and compares a 10-transistor 1-bit complete circuit to alternatives that employ 20 and 14 transistors.
Microwind 3.1, a CAD program, was utilized for every circuit simulation.
Reductor layout for feature size The 90nm technology has been applied to determine the values of certain parameters.
The energy efficiency of the suggested 10-transistor complete subtractor is higher than that of its competitors.


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How to Cite
Kumar, S. N., & Porwal, D. M. K. (2020). EMBEDDED SYSTEM BASED 1-BIT FULL SUBTRACTOR FOR ARITHMETIC APPLICATIONS. Turkish Journal of Computer and Mathematics Education (TURCOMAT), 11(3), 2825–2837. https://doi.org/10.61841/turcomat.v11i3.14587
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