Efficient ATPG Technique for Multiple Single Input Change Test Designs in BIST for Improved Fault Coverage and Reduced Test Time
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Abstract
In the context of Built-In Self-Test (BIST) design, the Automatic Test Pattern Generation (ATPG) technique holds significant importance as a vital aspect. The successful execution of the task is contingent upon the utilization of an appropriate Automatic Test Pattern Generation (ATPG) technique. In this research, we present a novel technique for designing multiple single input change (MSIC) tests specifically intended for the sweep chain. In order to develop any methodology, it is necessary to take into account the spatial and temporal aspects of advanced Very Large-Scale Integration (VLSI) designs. Additionally, one must be capable of efficiently conducting testing using test-per-clock and test-per-scan techniques. The appropriate examination for the implementation of the Managed Service Innovation Center (MSIC) was also provided. The execution evaluation is conducted through the process of planning in VERILOG and utilizing simulation and synthesis tools such as Model-sim 6.6 and Xilinx 14.3. The output display and verification can be achieved by utilizing ISCAS benchmarks. The proposed technique offers effective fault coverage without increasing the complexity of built-in self-test (BIST) design and test duration.
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