DESIGN AND IMPLEMENTATION OF LOW AREA AND HIGH SPEED MODIFIED DLAU ARCHITECTURE ON FPGA
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Abstract
At present days, artificial intelligence plays an prominent role in the digital world. Machine
learning and deep learning are used to solve the complex problems which are facing in the
artificial intelligence. In artificial intelligence neural networks are the basic building blocks to
operate any operation. Hence high speed and energy efficient deep learning neural networks
are needed. To achieve this scalable deep learning accelerator unit (DLAU) is implemented
for large scale architectures. The proposed DLAU used in the carry save adder for the
calculation process and to verify the performance analysis. The experimental results shows
that the proposed design achieves high speed and the performance is high compared to the
other architectures
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