A MODIFIED PARTIAL PRODUCT GENERATOR FOR REDUNDANT BINARY MULTIPLIERS (Turkish Journal of Computer and Mathematics Education (TURCOMAT), 2021)
Approximate computing can decrease the design complication with an increase inperformance and power efficiency for error tolerant applications like multimedia signal processing anddata mining which can tolerate error, exact computing units is not always necessary. They can bereplaced with their approximate counterparts. A new design approach for approximation of multipliersbased on partial products is altered to introduce varying probability terms. A high speed approximateredundant binary multiplier is designed by using two redundant binary 4:2 compressors. Thencomparison in terms of power, delay, area and signal rate of approximate redundant binary multiplier(using conventional modified booth algorithm) with high speed approximate redundant binary multiplieris done using Xilinx tool. In Existing system, Implementation of multiplier comprises three stepsgeneration of partial products, partial products reduction tree, and vector merge addition to produce finalproduct from the sum and carry rows generated from the reduction tree. Second step consumes morepower. To reduce power and improve approximate difference, a novel compressor based approximatemultiplier is proposed.