FPGA Implementation of Efficient VLSI Architecture of DLMS Adaptive Filter Algorithm (Turkish Journal of Computer and Mathematics Education (TURCOMAT), 2021)
In this Paper, an efficient implementation of the direct form of the least mean square (LMS) adaptive filteralgorithm is proposed. The conventional multiplier hinders the speed of the delayed LMS (DLMS) algorithm;hence latest high speed Vedic Multiplier is used for its high convergence rate, further, the Vedic Multiplier isexplored for reducing the number of logic levels and timing levels, and possible reduction in logic delay. Theefficient adders are used in digital signal processing applications to reduce the power requirement, area anddelay. Vedic Multiplier and different adders (such as carry-increment, carry-look ahead, carry-select, ripplecarryand carry-skip adder) used to implement the DLMS algorithm are compared (a) with ripple-carry adderand vedic multiplier, (b) with vedic multiplier and carry-look ahead adder, (c) with Vedic multiplier and carryskipadder, (d) with Vedic multiplier and carry-increment adder, with (e) Vedic multiplier and carry-selectadder based on their delay. Xilinx ISE is used for simulation and synthesis of the design with Spartan-6 FPGA,XC6SLX4-2TQG144.