Performance analyzes of RNS-FIR filter using prefix accumulation based DA arithmetic (Turkish Journal of Computer and Mathematics Education (TURCOMAT), 2022)
This study describes the design of high speed FIRfilter design with low complexity using various types of adders andmultiplication methods. This work also explores the significanceof prefix addition in path delay reduction and it’s acceleratingperformance in various DSP applications. The FIR filters consistof two core functional units such as adder and multiplier. In manyexisting FIR filter designs the system performances areaccelerated using various multiplication methodologies and someoptimization techniques. This paper briefly investigates thenecessities of the parallel prefix adder in path delay reductionsand the influence of multiplier less FIR design in overall systemperformance. And conclude the performance metrics and tradeoff measures between complexity and path delay optimizationlevel of various types of Prefix adders and multipliers. This workfocuses on both high speed accumulation and multiplication unitsfor high performance FIR filter design and its performance iscompared with the existing FIR filter design in terms of delay andhardware utilization rate.