(untitled) (Turkish Journal of Computer and Mathematics Education (TURCOMAT), 2021)
Multilevel inverters are extensively implemented in high power and voltage applications because of its lower THD, lower switching stress over its switches etc. However, to obtain to lower THD the number of stages has to be increased. As a result, the size becomes bulky. Hence, to reduce this problem, this work formulated a new 7 level CMLI with reduced switches. This topology designs 7 level MLI with 6 switches and produce same output as that of conventional one. SVPWM technique is instigated to generate gate pulse to the switches. Finally the performance of this designed work is validated in MATLAB simulation. From the analyzed results, it is found that this proposed topology. Will results in better harmonic reduction, with lower number of switches.