Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flipflop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS.


Introduction
In a recentscenario,theInternet of Things (IoT) is the most emerging area in the era of healthcare and smart environments. IoT constitutes the vital components like objects & sensors. IoT devices mostly use the battery as a power source for their desired operation.It requires devices with maximum battery life, high speed and portable.The battery life is improved with a low voltage operation called voltage scaling. The speed of thesedevices is increased by minimizing un-necessary delays [1], [2]. These devices become portable by scaling down the length of the transistors to an optimum size. Several methods are utilized for low voltage operation and are achieved by sub-threshold techniques.
IoT devices utilize memory elements for data processing applications in various fields. Memory elements may be either a latch or a flip-flop. Flip-flops are the most vital components for present circuit design to store 1bit of data. Flip-flops are sensitive to edges of the clock to perform storage operations. Besides storage, flip-flops are also used to synchronize the data flow. Hence, the synchronization is done throughout the entire clock [3]. A huge number of flip-flops are used in a regular processor, frequently many thousands. flip-flops involve an enormous part of the general circuit, decreasing power utilization has an extraordinary impact on system-level energy efficiency [4]. Particularly for energy-compelled IoT applications. Reducing power utilization in IoT integrated circuit is significant for increasing battery life. But flip-flops which are switch by every clock cycle, consume a huge part of the dynamic power in an organized system. Therefore, many experimenting works have been performed to create flip-flops with lower power utilization and better energy proficiency.
The most recommended procedure for a flip-flop is utilizing either the rising or falling edge of the clock as atrigger source for the switching operation. This kind of flip-flop is known as a Single-Edge-Triggered flip-flop (SET-FF) [1], [5], The other form of flip-flops are Dual edge-triggered flip-flops (DET-FF) use the both rising & falling edge of the clock to perform the desired operation. Utilization of both clock edges accomplishes better energy proficiency because it latches the data for both the edges. Therefore, the throughput of DET-FFis maximum than SET-FF compared at the same clock frequency. Hence, the DET-FFis proposed as an alternative sequential circuit element for low power utilization compared to SET-FF [6], [7].
SET FF & DET FF are realized by using severaldynamicCMOS logic styles like C-CMOS, Domino, N-P MOS, Dual threshold CMOS, Multi threshold CMOS, LVCMOS, TSPC logic. Of these, True single-phase clock (TSPC) logic-based flip-flopsdiminish the leakage current generated at the dynamic nodes and utilize the wide operational frequency range in the CMOS process. TSPC also performs the flip-flop operation with low power, delay and high clock speed [8] [9]. TSPC logic uses a single-phase clock to implement the latches and these latches are non-inverting. In TSPC logic, the functionality is embedded into the latch which reduces delay overhead provided by the latches.
In this paper, DET-FF's are realized by using TSPC logic because of its advantages compared with remaining logic styles. DET-FF's are implemented with TSPC by using both AND-OR logic and TRANSMISSION GATES at the output side as a MUX to produce necessary output Q. It provides a comparative analysis of both the flip-flops in terms of reliable parameters like power, latency and figure of merit (FOM). It also deduces the best DET-FF that suits IoT applications.
Meantime, a simple and widely designed technique is used for maximizing the energy efficiency in the electronic system is voltage scaling. By diminishingsupply rail voltage VDD, a quadratic drop in dynamic energy utilization was observed. Hence, voltage scaling can be widely used for the less energy-constrained IoT applications.

Proposed Art
The proposed art entitles Full Static-True Single-PhaseClock-Dual Edge Triggered Flip-Flop (FS-TSPC-DET-FF) that acts as Data Flip-Flop (D-FF) is implemented with TSPC logic and developed in 45nm CMOS technology using AND-OR logic & Transmission gate MUXas the output drivers to provide full voltage swing at the output node Q. It also provides a compact size flip-flop for portable IoT applications [10], [11].
Data Flip-Flopsarecommonlydesigned by using latches in cascaded nature.Latches that are usually available are positive latch and negative latch cascaded together to form a flip-flop or a register. Fig 1. shows the positive and negative latches cascaded together to form a D-flip-flop with D as its input, Q as the output. The operation of the D-FF signifies that the output is identical to the input. D-FF proposed in this era uses only a single-phase clock to carry out its operation [10], [12]. It presents the desired operation on both the edges of the clock (rising & falling edges).These latches are encapsulated with theoutput drivers like AND-OR gate, transmission gate MUXthatoperatesasDualEdge Triggered -Flip-Flop (DET-FF).

CDN=(DN.CLK)' (2)
The critical node values CDP, CDN depends on the QP, QN values generated from positive & negative latches respectively [10].The output node Q is obtained with the help of CLK, QP & QN as stated below in equation (3).

Q= QN.CLK+QP.CLK' (3)
As CLK='0' & D='0', the critical nodes are pre-charged to HIGH logic with CDP = CDN ='1', At the same time, the output node Q holds the previous state that is located at '0'. As the CLK only changes its transition from '0' to '1' and consider 'D' remains uniform that results in the changes of critical nodes CDP & CDN as CDP=CDN='0' and latches the output node Q ='0'.

Figure 2. TSPC DET-FF with TG-MUX
The circuit proposed in figure2 operates similarly to the circuit that is proposed in figure 1 up to the output driver stage. AND-ORoutput driver stage in figure 1 is replaced with transmission-gate based MUX to latch the QP, QN outputs to the output node Q. FS-TSPC DET-FF is proposed on MUX based topologyto allow CLK & CLKI to perform the D-FF operation. CLKI is the delayed CLK to overcome clock overlap issues during the operation. The use of CLKI in the figure2 makes the circuit operate efficiently compared with figure1. CLK & CLKI are primarily used to enable both the positive & negative latches at the same time to enhance the speed. A transmission gate-basedMUX, controlled by a two-phase clocklatch the data from both the latches to output node Q with minimized constraints [10], [15].
The transmission-gate MUX selects either QP or QN based on the selection line CLKB. As CLKB ='0', the output node Q=QP. and CLKB ='1', the output node Q=QN. CLKB is the inversion of the CLK to perform latching of the data from QP, QN to output node Q without disturbing the latch operation.
FS-TSPC DET-FF implemented with AND-OR logic circuit indicated in figure1 suffers from several conslikemore power and low speed of operation during the simulation. The cons specified across AND-OR logic is diminished by transmission-gate MUX. Figure2 also overcomes all clock overlap issues that were recognized in the existing circuits.

Results and Discussion
This section entitles the simulations carried out in the MENTOR GRAPHICS tool, cons that are observed in AND-OR logic, pros by using transmission-gate MUX, comparative analysis of both the circuits at circuit level in terms of several parameters, like, Power, Speed, Figure of Merit, etc. It recognizes the best-proposed latch to carry out desired IoT applications.
The simulation wascarried out using the MENTOR GRAPHICS tool using 130nm, 90nm, 45nm CMOS process with VDD= 1V at 27 O C temperature for both AND-OR logic& transmission-gatebased MUX latches are mentioned in figures 1 & 2. ELDO Simulator is used to carry out simulations to reckon the parameters like power, latency and figure of merit for each technology parameter. Simulated waveforms of the AND-OR logic &transmission-gate-based MUX latches are shown in figures3 & 4 respectively [10], [17].Figures3 & 4 represent the simulated waveforms of AND-OR logic & transmission-gate-based MUX latches that use CLK as the control signal to latch the input D to the output node Q. It is noticed that output Q of the AND-OR logic in figure3 suffers from glitches that increase the power dissipation of the latchand also degrade the output logic levels [10], [18], . Figure4 presents the output waveform of the transmission-gate based MUX latch with glitch-free that diminishes the power dissipation and enhances the speed of operation to a great extent. The waveforms in figure3 & 4 are simulated at a 45nm CMOS process.    From Equation (4), CL dictates load capacitance of the latch at output node Q, VDD dictates the supply voltage of the latch and f dictates the frequency of operation for the latch.   [10], [19]. It also dictates that as the technology scales down the parameters like power, latency & figure of merit also scale down respectively.

Conclusion
The conclusion dictates that transmission-gate MUXbased Fully static True single-phase Dual edge-